1. Field of the Invention
The present invention relates in general to a nonvolatile memory cell (NVM cell). In particular, the present invention relates to a self-aligned dual-bit NVM cell and method for forming the same.
2. Description of the Related Art
The process of creating NVM cells is shown in FIGS. 1A, 1B and 1C. The ONO layers 10, 12 and 14 must be laid down on the p-type silicon substrate 16 and then etched to the desired size and shape. The etching is produced by first patterning a layer of photoresist 18 on top of the ONO layer in the places where the ONO is desired. An etch operation is then performed, to remove the upper oxide and nitride layers 14 and 12, respectively, but the etch affects only the places where there is no photoresist. The cells 20 of ONO are defined after etching.
As shown in FIG. 1B, an implant operation occurs (shown by arrows 30) which implants ions, such as Arsenic or Phosphorous, into the areas between the cells 20. This creates n-type source and/or drain areas 32 for the memory array cells in the p-type silicon substrate 16. The source/drain areas 32 are called bit lines.
As shown in FIG. 1C, a pocket implant 34 is provided at an angle to the right of vertical to form the left bit line junctions 36 of the channels.
As shown in FIG. 1D, another pocket implant 38 is provided at an angle at the same angle as before; however, for the right bit line junctions 40 of the channels, the implant angle is to the left of vertical.
After the lower oxide layer 10 and the photoresist 18 are removed, a thick bit line oxide 24 is then grown (FIG. 1E) between neighboring cells 20 to protect bit lines 32 and to electrically isolate neighboring cells 20.
Such NVM cells can store dual bit data in one cell, with one bit on either side of the cell, as shown in FIG. 2. The cell has a single channel 42 between two bit lines BL1 and BL2 but two separate and separately chargeable areas 12a and 12b. The chargeable areas 12a and 12b are within the nitride layer 12, and each chargeable areas 12a and 12b stores one bit.
Unfortunately, the charges stored in the chargeable areas 12a and 12b within the nitride layer 12 may disturb each other.
The object of the present invention is to provide a dual-bit NVM cell that can prevent the chargeable areas within the nitride layer from disturbing each other.
Another object of the present invention is to provide a method of forming the self-aligned dual-bit NVM cell, which can prevent the chargeable areas within the nitride layer from disturbing each other.
To achieve the above-mentioned object, the present invention provides a dual-bit NVM cell comprising a channel, two bit lines disposed on either side of the channel in columns, two isolation lines disposed on the bit lines, a control gate located over the isolation lines and on the channel in rows, a passivation layer disposed under the control gate, two isolated chargeable areas composed of nitride disposed on either side of the channel, a bottom oxide layer, and a top oxide layer. The control gate and the passivation layer are disposed over and between the two isolated chargeable areas. The bottom oxide layer is disposed over the bit lines and the channel and under the chargeable areas, the isolation lines and the passivation layer. The top oxide layer is disposed over the chargeable areas and under the isolation lines and the passivation layer. The isolated chargeable areas are located between the top oxide layer and the lower oxide layer.
A method for forming a dual-bit NVM cell is also provided. An oxide-nitride-oxide (ONO) layer is formed on a substrate, wherein the ONO layer is formed of a bottom oxide layer, a nitride layer, and a top oxide layer. A mask layer is formed on the ONO layer in columns. Bit lines are formed in the substrate using the mask layer as an implanting-obstructed layer. An isolation layer is formed between the mask layers in columns, which are then removed. A polymer layer is coated on the isolation layer, wherein the thickness of the polymer layer at the top and sidewall of the isolation layer is far greater than at the top oxide layer. The top oxide layer and the nitride layer are etched so as to define the nitride layer between the isolation layer into two isolated chargeable areas, and the polymer layer is then removed. Rows of control gate are formed perpendicular to the bit lines and on the isolation layer and the ONO layer.